1. Field of the Invention
The present invention relates to a precise polishing apparatus and a precise polishing method for polishing a substrate such as a wafer with high accuracy.
2. Related Background Art
Recently, fine arrangement and multi-layer wiring of semi-conductor devices have progressed, and, thus, there is a need to provide precise polishing apparatuses for accurately flattening a surface of a semi-conductor wafer made of Si, GaAs, InP or SOI or a glass or quartz substrate (so-called element substrate) having a transistor. Among them, as a precise polishing apparatus for accurately flattening the surface of the substrate such as a wafer on which semi-conductor elements are formed, a chemical mechanical polishing (CMP) apparatus is known.
Conventional CMP apparatuses can be divided into two types shown in FIGS. 7 and 8.
(1) FIG. 7 is a schematic view of a polishing work portion of the CMP apparatus in which the polishing (abrasion) is effected with a polished surface of a wafer 100 facing downwardly.
As shown in FIG. 7, the wafer 100 is held with the polished surface (surface to be polished) thereof facing downwardly, and the wafer 100 is polished by urging the wafer against a polishing pad 502 having a diameter larger than that of the wafer while rotating the wafer. During the polishing, abrasive agent (slurry) is supplied onto the polishing pad 502.
In the apparatus of this kind, holding the wafer onto a wafer chuck 501 by using vacuum suction or adhesion by using wax, solution or pure water have been adopted. Additionally, in some cases a guide ring is provided on a periphery of the wafer 100 to prevent deviation of the wafer 100. The diameter of the polishing pad 502 on a polishing table 506 is greater than that of the wafer 100 by 3-5 times, and suspension obtained by mixing fine powder of silicon oxide with solution of potassium hydroxide is used as the slurry.
(2) On the other hand, as shown in FIG. 8, there has been proposed a technique in which a wafer 100 is held on a wafer chuck 601 having a guide ring and disposed on a wafer table 606 with a polished surface thereof facing upwardly and the wafer 100 is polished by using a polishing pad 602 having a diameter smaller than that of the wafer 100.
In such polishing apparatus and method, the substrate such as the present semi-conductor wafer having a diameter of eight inches can be polished exclusively. However, recently, since fine arrangement of semi-conductor integrated circuits and large diameter wafers have been proposed, it is guessed that the wafer having 8-inch diameter will be replaced by a wafer having 12-inch diameter in the near future.
However, in such conventional polishing apparatuses, although the polishing ability is adjusted by making a thickness and elasticity of the polishing pad optimum to polish the 8-inch wafer, in this case, it is difficult to ensure fine adjustment and uniformity of material of the polishing pad, and, thus, it is very difficult to polish the large diameter wafer such as a 12-inch wafer with high accuracy.
In order to solve the above problem, it is considered that the entire surface of the wafer is firstly polished by using a rough polishing pad, and, then, a desired portion of the wafer is polished selectively or preferentially to obtain a desired wafer surface.
However, in order to polish the large diameter wafer (having the diameter of 8 inch or more), there arises the following problem in the conventional techniques.
In the conventional polishing apparatuses and methods using a polishing tool greater than the wafer, a portion of the wafer which could not be made uniform is very hard to be made more uniform or be further flattened by using the same method. Further, in a system in which a polishing tool smaller than the wafer is used and scan is effected while oscillating the rotating polishing tool or in a system in which a polishing tool smaller than the wafer is used and scan is effected while revolving the rotating polishing tool within a radius range greater than a radius of the tool and oscillating the tool, although a desired portion of the wafer can be polished selectively or preferentially, pitch unevenness due to the scan is apt to be generated, and, it is difficult to correct such pitch unevenness with high accuracy and to make the wafer surface uniform and to flatten the wafer surface. Also in a system, as disclosed in U.S. Pat. No. 4,128,968, in which a rotating and revolving tool having a sectional configuration of the polishing becoming maximum around a revolution axis and gradually decreasing toward the periphery is used, although a desired portion of the wafer can be polished selectively or preferentially, pitch unevenness due to the scan is apt to be generated, and, it is difficult to correct such pitch unevenness with high accuracy and to make the wafer surface uniform and to flatten the wafer surface.